As a data holding circuit for use in the sequential circuit such as the latch circuit, a circuit made by for example connecting two inverter circuits in a series loop is known. Such a data holding circuit, however, usually can hold data only in volatile manner, and so the data are lost when power supply is stopped. That is to say, even if the power supply is resumed, the previous data cannot be restored.
Therefore, for example when a sequential process using such a sequential circuit must be suspended for any reason, the power supply must be maintained to hold the data. Accordingly electric power is consumed. In the case the sequential process is interrupted due to power failure or the like, the process must be redone from scratch, incurring much loss of time.
To solve such a problem, a circuit 901 shown in FIG. 11 using a ferroelectric capacitor has been proposed. With the circuit 901, input data D are latched with a data latch circuit 902 by a fall of a clock pulse CK.
When a writing signal is given to the plate line PL in the state of the data latched, paired ferroelectric capacitors 911 and 913 are respectively set to a polarized state corresponding to the latched data. Even if the power supply is shut off thereafter, residual polarization corresponding to the data is held with the ferroelectric capacitors 911 and 913.
After that, first, when a reading signal is given to the plate line PL before resuming power supply, a voltage corresponding to the residual polarization held is produced at one ends 911a and 913a of the ferroelectric capacitors 911 and 913. After that, when power supply is resumed, the previous data based on the produced voltage are restored with the data latch circuit 902. In this way, the data before the stop of power supply are restored.
However, the above circuit 901 has problems as described below. When the clock pulse CK is “H,” while the input data D are inputted to the data latch circuit 902, the potential of the input node 907a of the inverter circuit 907 does not change immediately because one end 911a of the ferroelectric capacitor 911 is connected to the input node 907a of the inverter circuit 907.
Therefore, if the frequency of the clock pulse CK is high, it is hard to accurately latch the input data D. This makes it hard to use such a circuit in devices that are required to function at high speeds.
Another problem associated with the above circuit 901 is as follows. As for the p-MOSFET (p channel MOSFET) 915 constituting an inverter circuit, such as an inverter circuit 909, contained in the data latch circuit 902, as shown in FIGS. 12A and 12B, its well region 919, together with the source region 921, is connected to the power supply line VDD.
That is to say, the well region 919 before resuming power supply is like the source region 921 in the state of high impedance. Therefore, even if a large amount of electric charge is released from one end 911a of the ferroelectric capacitor 911 by giving a reading signal to the plate line PL before resuming the power supply, most of it ends up in moving from the drain region 923 through the PN junction 920 to the well region 919.
As a result, as shown FIG. 13, when a reading signal is given to the plate line PL, the difference between the voltage V1 produced at the one end 911a of the ferroelectric capacitor 911 when the ferroelectric capacitor 911 is inverted by polarization (for example corresponding to the data “H”) and the voltage V2 produced at the one end 911a of the ferroelectric capacitor 911 when the ferroelectric capacitor 911 is not inverted by polarization (for example corresponding to the data “L”) is not so large.
In other words, detection margin when data are restored by resuming power supply is small and so the reliability of restored data is low.